Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, medical, automobile, and other applications. The technology used to manufacture image sensors, and in particular CMOS image sensors, has continued to advance at great pace. For example, the demands of higher resolution and lower power consumption and cost have encouraged the further miniaturization and integration of the image sensor. Possibly as a result of the greater miniaturization and integration of the image sensor, various issues for both CMOS image sensors have arisen. For example, it is often difficult to maintain uniformity of performance across the millions of pixels in an image sensor pixel array.
Currently, the most popular type of CMOS pixel structure is the four transistor active pixel. FIG. 1 shows a cross-sectional view of a prior art active pixel that uses four transistors. This is known in the art as a 4T active pixel. A photodiode 101, outputs a signal that is used to modulate an amplification transistor 103. The amplification transistor 103 is also referred to as a source follower transistor. In this embodiment, the photodiode 101 can be either a pinned photodiode or a partially pinned photodiode. The photodiode 101 comprises a N− layer 115 that is a buried implant. Additionally, in one embodiment, a shallow P+ pinning layer 116 is formed at the surface of the semiconductor substrate 102.
Further, various structures are formed atop of and into the silicon substrate 102. For example, the photodiode 101 and the floating node 107 are formed into the silicon substrate 102. These structures are said to be formed below the surface of the silicon substrate by the use of dopants. Similarly, field oxides or shallow trench isolation structures are also formed at and below the top surface (or simply surface) of the silicon substrate. Other structures, such as the gate oxide 108, the transfer gate 106, the transfer transistor 105, and the reset transistor 113 are formed atop of the silicon substrate 102 and are said to be at or above the top surface of the silicon substrate.
A transfer transistor 105 is used to transfer the signal output by the photodiode 101 to floating node 107 (N+ doped), which is adjacent to the gate of the transfer transistor 105 and opposite the photodiode 101. The transfer transistor 105 is controlled by a transfer gate 106. The transfer transistor 105 also has a gate oxide 108 underneath the transfer gate 106.
In operation, during an integration period (also referred to as an exposure or accumulation period), the photodiode 101 stores charge that is held in the N− layer 115. After the integration period, the transfer transistor 105 is turned on to transfer the charge held in the N− layer 115 of the photodiode 101 to the floating node 107. After the signal has been transferred to the floating node 107, the transfer transistor 105 is turned off again for the start of a subsequent integration period. The signal on the floating node 107 is then used to modulate the amplification transistor 103.
In the prior art, the photodiode 101 and its implants 115 and 116 are typically not self-aligned to the adjacent transfer gate. Thus, the surface P+ implant 116 and the buried N− implant 115 oftentimes may or may not be aligned with the transfer gate 106. In the prior art, both of these implants are performed prior to the formation of the transfer gate 106. For example, turning to FIG. 2, after the active areas and shallow trench isolations (STI) are formed, a photoresist is patterned over the gate oxide layer. The photoresist has an opening that allows for the formation of the surface P+ implant 116. The P-type implant, typically boron, is then implanted in the opening forming the surface P+ implant layer 116. The resist is then stripped.
Next, in FIG. 3, new photoresist layer is patterned. An N-type implant, such as phosphorous, is implanted in the opening forming the buried N− implant layer 115. Note that the lateral offset between the P+ layer 116 and the N− layer 115 varies due to alignment registration errors at both of these patterning steps. Next, a gate oxide and a transistor gate stack are formed on the wafer. A spacer layer is deposited and etched back using an anisotropic etch and the source/drain regions are implanted as shown in FIG. 1.
The overlap of the N− implant under the adjacent transfer gate and the underlap of the P+ implant 116 to the transfer gate are controlled by alignment registration of the P+ implant reticle, the N− implant reticle, and the transistor gate reticle. This introduces a variability in both the performance of the transfer gate and for charge transfer from the photodiode to the floating node 107.
Further, using conventional steps, the N channel and P channel lightly doped drain (LDD) implants are performed. The LDD implants are masked implants with resist covering the photodiode region so that the photodiode is not implanted. Sidewall spacers are formed such that the N+ and P+ source/drains can be implanted as seen in FIG. 1.
Next, turning to FIG. 4, in the prior art, in a salicide process, a protective insulator is deposited typically with a thickness of 100-1,000 Å of oxide. The protective insulator is removed from the gate stack using either a resist etch back process or a chemical-mechanical polishing (CMP) process. The result after the removal step is seen in FIG. 5. Next, in FIG. 6, a photoresist layer is formed which protects the photodiode. A metal such as cobalt or titanium is then deposited onto the wafer to a thickness of between 50-300 Å. A heat treatment is performed to allow the silicon in contact with the metal to react to form a metal silicide. Finally, the wafer is wet dipped into a bath that removes the unreacted metal and the result is seen in FIG. 7. Remaining process steps to complete the imager include dielectric deposition, contact etching, metal and via formation, passivation, bond pad etching, color filter arrays formation, and microlens formation.
As seen above, the prior art process may result in inconsistent lateral offsets between the photodiode and the transfer gates due to alignment issues.